1. Field of the Invention
The present invention relates to a high-voltage MOS (HV MOS) transistor device, and particularly, to a HV MOS transistor device having a P doped region positioned in an N ion well and a plurality of field plates to produce a smooth field distribution when subject to a high drain voltage and prevent the HV MOS transistor device from breakdown.
2. Description of the Prior Art
Current power systems provide an alternating current having a variety of frequencies ranging from 50 to 60 Hz, and a voltage ranging from 100 to 240 volts (V). Every electrical device has a particular working voltage and frequency condition, and therefore, electrical devices and related passive elements utilized in the electrical devices, such as inductors, capacitors, resistors and transformers, act as a switch to determine the value of the voltage and the type of the current thereof. For example, a conventional air conditioner utilizes a power supply providing a low-voltage current for the inner facilities. The power supply switch reduces the voltage provided by the outer power system to an appropriate voltage for the inner facilities. In addition, the power supply switch has the characteristics of high efficiency, low weight, small size and reduced power consumption. High-voltage metal-oxide semiconductor (HV MOS) transistor devices may function as switches and are broadly utilized in CPU power supplies, power management systems, AC/DC converters, LCD/plasma TV drivers, automobile electronic components, PC peripheral devices, small DC motor controllers, and other consumer electronic devices.
Here, the structure of a prior art HV MOS transistor device is described briefly. Please refer to FIG. 1. FIG. 1 is a schematic diagram of a prior art HV MOS transistor device 1. The HV MOS transistor device 1 is formed on a semiconductor substrate 2. The HV MOS transistor device 10 has a source 3, a gate 4, and a drain 5. The source 3 is positioned next to a heavily P doped region 6. Both the source 3 and the heavily P doped region 6 are formed in a P-type well 7. The drain 5 is formed in an N well 8 that is formed in a deep N well 9, forming a triple-well structure. As shown in FIG. 1, a gate dielectric layer 10 is formed on the source 3. The gate 4 is disposed on the gate dielectric layer 10 and extended to approach a field oxide 11 disposed between the source 3 and the drain 5. The active area of the HV MOS transistor device 1 is isolated by a plurality of field oxide layers 12 from other devices formed on the same semiconductor substrate 2. In addition, another HV MOS transistor device, in which a P doped region is used inside the N well, is disclosed. The device is optimized to increase the breakdown voltage thereof. However, the power source supplied by the outer voltage source is an AC power. The usual waveform of an AC power circuit is a sine wave, and a 240V AC power may alter its voltage from −300V to +300V. The voltage may be over 600V in an instant. This is greater than the breakdown voltage of most HV MOS transistor devices in the field and leads to HV MOS transistor device damage. Therefore, an HV MOS transistor device capable of withstanding high voltages is required.